A Field Programmable Gate Array (FPGA) is a device known for its capability of electrically modifying the design of the digital circuit. An FPGA is a Large Scale Integration circuit (LSI) having many logic gates and functions as an intended logic circuit by writing configuration data describing therein logical and connection relationships among logic gates into a configuration RAM that the FPGA has.
Using FPGAs as the circuit parts of various electronic devices makes it possible to shorten the time that the circuit implementation takes as compared with cases where circuit parts are manufactured according to circuit design. Further advantageously, the circuit design can be easily modified simply by modifying the configuration data, not requiring a change in hardware.
FPGAs are used in wide variety of products as well as in electronic devices. As one of the usages, there has been known a power-failure dealing system being mounted on a server computer and being equipped with an FPGA in which system the FPGA achieves backup of Dual Inline Memory Module (DIMM) data.
FIG. 9 is a block diagram schematically illustrating the configuration of a typical power-failure dealing system.
The typical power-failure dealing system of FIG. 9 includes a Central Processing Unit (CPU) 501, a peripheral device 502, a memory controller 503, a monitoring FPGA 504, a DIMM 505, a storage device 506, and a power-failure FPGA 507.
The CPU 501 is a processor that carries out various controls and calculations, and specifically achieves various functions by executing the Operating System (OS) and a program.
The peripheral device 502 is a hardware device exemplified by a display device, an I/O controller, and an interfacing device, and is communicably connected to the CPU 501 via an interface such as a Peripheral Component Interconnect Express (PCIe) interface.
The storage device 506 is exemplified by a Hard disk drive (HDD) and a Solid State Drive (SSD), and stores therein various pieces of data.
The DIMM 505 is a storing region that stores therein various pieces of data and a program. When the CPU 501 is to execute a program, data and the program to be used in the execution are stored and expanded in the DIMM 505. In the event of power failure, a copy of data stored in the DIMM 505 is stored (i.e., backed up) in the storing device 506.
The memory controller 503 manages data access to the DIMM 505 for reading data from or writing data into the DIMM 505.
The monitoring FPGA 504 detects power failure, and when detecting the occurrence of power failure, controls to halt power supply to the CPU 501 and the peripheral device 502. In the event of power failure, a non-illustrated standby power source such as a super capacitor supplies electric power to the memory controller 503, the monitoring FPGA 504, the DIMM 505, the storage device 506, and the power-failure FPGA 507.
A power-failure FPGA 507 controls, in the event of power failure, to back up data in the DIMM 505 into the storage device 506 via the memory controller 503 by means of Direct Memory Access (DMA).
In the typical power-failure dealing system 500 of FIG. 9, even when power failure occurs, the presence of a standby power source makes it possible to continue power supply to the memory controller 503, the monitoring FPGA 504, the DIMM 505, the storage device 506, and the power-failure FPGA 507.
Then the power-failure FPGA 507 backs up data in the DIMM 505 into the storage device 506 via memory controller 503 by means of DMA. Namely, when power failure occurs, the power-failure FPGA 507 backs up data in the DIMM 505 totally independently from the CPU 501, being supplied with power from the standby power source. Hereinafter, backing up data in the DIMM 505 into the storing device 506 during power failure is sometimes referred to as “power-failure backup”.
In contrast, during power failure, power supply to the CPU 501 and the peripheral device 502 is stopped to reduce power consumption of the standby power source.
As one solution to reduce the manufacturing cost of the above power-failure dealing system 500, relatively expensive FPGAs are omitted in the configuration of the power-failure dealing system 500.
In cases where the power-failure FPGA 507 is omitted, the standby power source supplies also the CPU 501 with power and the CPU 501 executes the firmware to achieve the function as the above power-failure backup.
Even in cases where power is supplied to the CPU 501 during the power failure, it is preferable to halt the power supply to the peripheral device 502, which consumes a relatively large amount of power.
[Patent Literature 1] Japanese Laid-open Patent Publication No. 2011-232986
[Patent Literature 2] Japanese Laid-open Patent Publication No. 2012-234539
[Patent Literature 3] Japanese Laid-open Patent Publication No. 2013-33472
[Patent Literature 4] Japanese Laid-open Patent Publication No. 2009-93295
However, the peripheral device 502 has a process being executed therein at the time of occurrence of power failure in the typical power-failure dealing system 500 that omits the power-failure FPGA 507 as the above, there is a possibility that an access to the peripheral device 502 is generated during the execution of the power-failure memory backup. Such an access to the peripheral device 502 is generated by the CPU 501 executing a device driver for the peripheral device 502.
When an access to the peripheral device 502 is generated under a state where no power is supplied to the peripheral device 502, a fatal error occurs in the system and a notification of NonMaskable Interrupt (NMI) is issued to the CPU 501. There is a possibility of not successfully executing the power-failure backup.